Module Title:   Digital Design using High-Level Description Languages

Module Credit:   10

Module Code:   ENG3051M

Academic Year:   2015/6

Teaching Period:   Semester 2

Module Occurrence:   A

Module Level:   FHEQ Level 6

Module Type:   Standard module

Provider:   Engineering

Related Department/Subject Area:   PI - Engineering: Telecomms, Electromagnetics etc (MDIS) (not in use)

Principal Co-ordinator:   Dr J M Noras

Additional Tutor(s):   -

Prerequisite(s):   None

Corequisite(s):   None

Aims:
Critical review of the concept of digital system design using high-level description languages and development of skills in their application.

Learning Teaching & Assessment Strategy:
Concepts, principles and theories explored in formal lectures, practiced in tutorials and demonstrated in laboratory classes. Practical skills developed in laboratory sessions. Cognitive and personal skills developed in open-ended problem solving and design exercises, tackled by working in small groups supported by members of academic staff. Oral feedback is given during labs and seminars. The laboratory assessment will assess students` grasp of the formal knowledge base of the module, the design exercise will assess the wider learning outcomes expressed in the descriptor. Supplementary assessment is to repair deficiencies in original submission.

Lectures:   16.00          Directed Study:   76.00           
Seminars/Tutorials:   8.00          Other:   0.00           
Laboratory/Practical:   0.00          Formal Exams:   0.00          Total:   100.00

On successful completion of this module you will be able to...

1.1 Evaluate critically the modern market place for electronic designs and implementations.
1.2 Appreciate the factors determining choice of DSP, ASIC, microprocessor and FPGA hardware solutions.

On successful completion of this module you will be able to...

2.1 Use high-level description languages to capture design requirements and implement hardware solutions.
2.2 Compare design languages and design platforms.
2.3 Synthesise and test computational structures.

On successful completion of this module you will be able to...

3.1 Analyse problem specifications.
3.2 Establish alternative design strategies and formulate testing criteria.

  Coursework   100%
 
  Portfolio of work comprising HDL syntax & semantics based lab assessment 1500wd equiv & design exercise 1500wd report

Outline Syllabus:
Introduction to High-Level description languages: overview of HDL as a design tool, revision of AHDL. VHDL: design entities, files and libraries, processes. Design Systems: Types, clocks and registers. Finite State Machine synthesis. Arithmetic functions and counters. Test benches, signals and simulation. Machine architecture: CISC, RISC and DSP. Computational structures and high-level design automation. Commercial issues: vendors, Xilinx and Altera, ASIC and FPGA, intellectual; property and design re-use.

Version No:  4